Public Thesis Defense of Najeh ZEIDI - ICTEAM
sst |
Integration of Large Passive Components on Silicon for High-voltage Galvanic Isolation
Monday April 13th, 2026 - 2pm - Auditorium SUD16 - Place Croix du Sud, 1 - 1348 Louvain-la-Neuve
The continuous increase in switching frequencies and power densities in power electronics necessitates galvanically isolated gate drivers to protect low-voltage circuits from high-voltage transients. Commercial isolators based magnetic transformers enable safe power transfer but typically occupy large areas on FR4 substrates and cannot transfer more than approximately 0.55 W to the high-voltage side. This power level is insufficient to supply the integrated circuits and sensors required to control modern wide-bandgap devices such as GaN and SiC transistors. Integrating galvanic isolation directly onto silicon substrates offers a promising approach to reduce system size, enhance performance, and increase transferable power. Such integration enables monolithic integration with gate driver circuitry, thereby reducing footprint, minimizing signal propagation delay, and mitigating parasitic capacitances and inductances associated with wire bonds. However, high power transfer requires thick metal layers to sustain large current densities, while robust isolation demands thick dielectric layers with high breakdown strength. Reconciling these conflicting requirements within standard silicon microfabrication processes constitutes a major technological challenge.
This thesis addresses these limitations through the design, fabrication, and characterization of an integrated on-chip transformer capable of delivering more than 1 W of power, while employing a thick dielectric layer exceeding 26 µm, designed to withstand surge voltages up to 10 kV and maintain a coupling capacitance below 2 pF at 200 MHz. First, high-resistivity silicon incorporating a trap-rich layer significantly enhances performance, increasing the inductor quality factor by more than 2.5×, capacitor performance by over 5×, and transformer efficiency by a factor of two, without additional post-processing. Second, a hybrid dielectric stack combining thick, low-stress polyimide layers exceeding 24 µm with thin inorganic barrier layers reduces leakage current by a factor of five compared to standalone polyimide, while maintaining a low dielectric constant of 3.2 to minimize coupling capacitance. Third, a hybrid transformer architecture featuring a non-spiral primary winding and a spiral secondary winding reduces losses and coupling capacitance, enabling power transfer exceeding 1 W. The integrated device occupies 5 mm² and operates at 200 MHz, delivering more than 1 W of power. The fabrication approach avoids complex post-processing steps and achieves accurate alignment between windings despite the thick dielectric layer.
This work demonstrates that high-performance integrated galvanic isolation with substantial power transfer is achievable using standard silicon microfabrication, paving the way for more compact and efficient power electronic systems.
Jury members
Prof. Denis Flandre (UCLouvain) (Supervisor)
Prof. Farès Tounsi (Université de Sfax, Tunisie) (Co-Supervisor)
Prof. Laurent Francis (UCLouvain) (Chairperson)
Prof. Jean-Pierre Raskin (UCLouvain) (Secretary)
Prof. Sami Gomri (ENETCOM) (Rapporteur)
Prof. Vincent Bley (UT3/UPS) (Examiner)